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SST29VF040-70-4C-NH 데이터시트(PDF) 1 Page - Silicon Storage Technology, Inc |
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SST29VF040-70-4C-NH 데이터시트(HTML) 1 Page - Silicon Storage Technology, Inc |
1 / 22 page ©2004 Silicon Storage Technology, Inc. S71160-10-000 2/04 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet 4 Mbit (x8) Small-Sector Flash SST29SF040 / SST29VF040 FEATURES: • Organized as 512K x8 • Single Voltage Read and Write Operations – 4.5-5.5V-only for SST29SF040 – 2.7-3.6V for SST29VF040 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 10 mA (typical) – Standby Current: 30 µA (typical) for SST29SF040 1 µA (typical) for SST29VF040 • Sector-Erase Capability – Uniform 128 Byte sectors • Fast Read Access Time: – 55 ns for SST29SF040 – 55 ns and 70 ns for SST29VF040 • Latched Address and Data • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 8 seconds (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility for SST29SF040 • CMOS I/O Compatibility for SST29VF040 • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST29SF040 and SST29VF040 are 512K x8 CMOS Small-Sector Flash (SSF) manufactured with SST’s propri- etary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29SF040 devices write (Program or Erase) with a 4.5-5.5V power supply. The SST29VF040 devices write (Program or Erase) with a 2.7- 3.6V power supply. These devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST29SF040 and SST29VF040 devices provide a maxi- mum Byte-Program time of 20 µsec. To protect against inadvertent write, they have on-chip hardware and Soft- ware Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 10,000 cycles. Data retention is rated at greater than 100 years. The SST29SF040 and SST29VF040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve perfor- mance and reliability, while lowering power consumption. They inherently use less energy during Erase and Pro- gram than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed dur- ing any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while low- ering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST29SF040 and SST29VF040 devices are offered in 32- lead PLCC and 32-lead TSOP packages. See Figures 1 and 2 for pin assignments. Device Operation Commands are used to initiate the memory operation func- tions of the device. Commands are written to the device using standard microprocessor write sequences. A com- mand is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. SST29SF/VF0404Mb (x8) Byte-Program, Small-Sector flash memories |
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