SSTUM32865_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 19 September 2007

9 of 28

NXP Semiconductors

SSTUM32865

1.8 V DDR2-800 registered buffer with parity

[1]

DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.

[2]

PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated

correctly.

[3]

This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched

LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ‘don’t care’ for PTYERR.

[4]

7.2 Functional information

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUM32865 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and undriven (floating) data, clock and

reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS

RESET input must always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUM32865 ensures that the outputs remain LOW, thus

ensuring no glitches on the output.

The device monitors DCS0, DCS1, DCS2 and DCS3 inputs and will gate the Qn outputs

from changing states when all DCSn inputs are HIGH. If DCSn input is LOW, the Qn

outputs will function normally. The RESET input has priority over the DCSn control and

will force the Qn outputs LOW and the PTYERR output HIGH. If the DCSn-control

functionality is not desired, then the CSGATEEN input can be hardwired to ground, in

which case, the set-up time requirement for DCSn would be the same as for the other Dn

data inputs.

The SSTUM32865 includes a parity checking function. The SSTUM32865 accepts a

parity bit from the memory controller at its input pin PARIN, compares it with the data

received on the Dn inputs (with either DCSn inputs active) and indicates whether a parity

error has occurred on its open-drain PTYERR pin (active LOW).