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Page 6 of 10

Issue A

LANSDALE Semiconductor, Inc.

ML145159

CHARGE

Ramp Charge Indicator (PDIP, SOG – Pin 4,

SSOP – Pin 9)

This output is high from the time fR goes high to the time

fV goes high (fR and fV are the frequencies at the phase detec-

tor inputs). This high voltage indicates that the ramp capacitor,

CR, is being charged.

FSO

Three–State Frequency Steering Output (PDIP,

SOG –Pin 6, SSOP – Pin 11)

If the counted down input frequency on fin is higher than the

counted down reference frequency of OSCin, this output goes

low. If the counted down VCO frequency is lower than that of

the counted down OSCin, this output goes high.

The repetition rate of the frequency steering output pulses is

approximately equal to the difference of the frequencies of the

two counted down inputs from the VCO and OSCin. See

Application Note AN969 for further information.

LD

Lock Detector Indicator (PDIP, SOG – Pin 9,

SSOP – Pin 14)

This output is high during lock and goes low to indicate a

non–lock condition. The frequency and duration of the

non–lock pulses will be the same as either polarity of the fre-

quency steering output.

MC

Dual Modulus Prescaler Control (PDIP, SOG – Pin 8,

SSOP – Pin 13)

The modulus control level is low at the beginning of a count

cycle and remains low until the divide–by–A counter has

counted down from its programmed value. At that time, the

modulus control goes high and remains high until the di-

vide–by–N counter has counted the rest of the way down from

its programmed value (N – A additional counts since both

divide–by–N and divide–by–A are counting down during the

first portion of the cycle). Modulus control is then set back

low, the counters preset to their respective programmed values,

and the above sequence repeated. This provides for a total pro-

grammable divide value of NT = N • P + A, where P and P + 1

represent the dual modulus prescaler divide values respectively

for high and low modulus control levels, N is the number pro-

grammed into the divide–by–N counter, and A is the number

programmed into the divide–by–A counter.

SRout

Shift Register Output (PDIP, SOG – Pin 14,

SSOP – Pin 19)

This pin is the non–inverted output of the last stage of the

32–bit serial data shift register. It is not latched by the ENB

line. If unused, SRout should be floated.

POWER SUPPLY

VDD

Positive Power Supply (PDIP, SOG – Pin 5, SSOP – Pin 10)

Positive power supply input for all sections of the device

except the analog phase detector. VDD and VDD’ should be

powered up at the same time to avoid damage to the

ML145159. VDD must be tied to the same potential asVDD’.

VSS

Negative Power Supply (PDIP, SOG – Pin 7,

SSOP – Pin 12)

Circuit ground for all sections of the ML145159 except the

analog phase detector. VSS must be tied to the same potential

as VSS’.

VSS’

Analog Phase Detector Circuit Ground (PDIP, SOG –

Pin 16, SSOP – Pin 1)

Separate power supply and ground inputs are provided to

help reduce the effects in the analog section of noise coming

from the digital sections of this device and the surrounding cir-

cuitry.

VDD’

Analog Power Supply (PDIP, SOG – Pin 19, SSOP – Pin 4)

Separate power supply and ground inputs are provided to

help reduce the effects in the analog section of noise coming

from the digital sections of this device and the surrounding cir-

cuitry.