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CD74HCT147 데이터시트(PDF) 1 Page - Texas Instruments |
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CD74HCT147 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 15 page 1 Data sheet acquired from Harris Semiconductor SCHS149F Features • Buffered Inputs and Outputs • Typical Propagation Delay: 13ns at VCC = 5V, CL = 15pF, TA = 25 oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l1 to l9) and provide binary representation on the four active LOW inputs (Y0 to Y3). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l9 having the highest priority. These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The “zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH. Pinout CD54HC147 (CERDIP) CD74HC147 (PDIP, SOIC, SOP, TSSOP) CD74HCT147 (PDIP, TSSOP) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC147F3A -55 to 125 16 Ld CERDIP CD74HC147E -55 to 125 16 Ld PDIP CD74HC147M -55 to 125 16 Ld SOIC CD74HC147MT -55 to 125 16 Ld SOIC CD74HC147M96 -55 to 125 16 Ld SOIC CD74HC147NSR -55 to 125 16 Ld SOP CD74HC147PW -55 to 125 16 Ld TSSOP CD74HC147PWR -55 to 125 16 Ld TSSOP CD74HC147PWT -55 to 125 16 Ld TSSOP CD74HCT147E -55 to 125 16 Ld PDIP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 I4 I5 I6 I7 I8 Y2 GND Y1 VCC Y3 I3 I2 I1 I9 Y0 NC September 1997 - Revised November 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC147, CD74HC147, CD74HCT147 High-Speed CMOS Logic 10- to 4-Line Priority Encoder [ /Title (CD74 HC147 , CD74 HCT14 7) /Sub- ject (High Speed CMOS Logic 10-to-4 Line Prior- ity Encode r) /Autho r () /Key- words (High Speed CMOS Logic 10-to-4 Line Prior- ity Encode r, High Speed CMOS Logic 10-to-4 Line Prior- ity |
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