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ADF4157BCPZ-RL71 데이터시트(PDF) 1 Page - Analog Devices |
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ADF4157BCPZ-RL71 데이터시트(HTML) 1 Page - Analog Devices |
1 / 20 page High Resolution 6 GHz Fractional-N Frequency Synthesizer ADF4157 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES RF bandwidth to 6 GHz 25-bit fixed modulus allows subhertz frequency resolution 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the following frequency synthesizers: ADF4110/ADF4111/ADF4112/ADF4113/ ADF4106/ADF4153/ADF4154/ADF4156 Cycle slip reduction for faster lock times APPLICATIONS Satellite communications terminals, radar equipment Instrumentation equipment Personal mobile radio (PMR) Base stations for mobile radio Wireless handsets GENERAL DESCRIPTION The ADF4157 is a 6 GHz fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT and FRAC registers define an overall N divider, N = INT + (FRAC/225). The ADF4157 features cycle slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM LOCK DETECT N COUNTER CP RFCP3 RFCP2 RFCP4 RFCP1 REFERENCE DATA LE 32-BIT DATA REGISTER CLK REFIN AVDD AGND VDD VDD DGND RDIV SDOUT NDIV DGND CPGND DVDD VP CE RSET RFINA RFINB OUTPUT MUX MUXOUT – + HIGH Z PHASE FREQUENCY DETECTOR ADF4157 THIRD ORDER FRACTIONAL INTERPOLATOR MODULUS 225 FRACTION REG INTEGER REG CURRENT SETTING ×2 DOUBLER 4-BIT R COUNTER CHARGE PUMP CSR ÷2 DIVIDER Figure 1. |
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