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P312XDP512J1VALR 데이터시트(PDF) 97 Page - Freescale Semiconductor, Inc

부품명 P312XDP512J1VALR
상세설명  Covers, S12XD, S12XB & S12XA Families
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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P312XDP512J1VALR 데이터시트(HTML) 97 Page - Freescale Semiconductor, Inc

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Chapter 2 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
97
2.3.2.12
CRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads 0x_00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than 0x_55 or 0x_AA causes a COP reset. To restart the COP time-out
period you must write 0x_55 followed by a write of 0x_AA. Other instructions may be executed
between these writes but the sequence (0x_55, 0x_AA) must be completed prior to COP end of
time-out period to avoid a COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes
are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of
the selected time-out period; writing any value in the first 75% of the selected period will cause a
COP reset.
76543210
R
00000000
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
00000000
Figure 2-15. ARMCOP Register Diagram


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