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74LVC4066PW 데이터시트(PDF) 3 Page - NXP Semiconductors |
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74LVC4066PW 데이터시트(HTML) 3 Page - NXP Semiconductors |
3 / 22 page 74LVC4066_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 27 August 2007 3 of 22 NXP Semiconductors 74LVC4066 Quad bilateral switch 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO14 and TSSOP14 Fig 5. Pin configuration for DHVQFN14 4066 1Y VCC 1Z 1E 2Z 4E 2Y 4Y 2E 4Z 3E 3Z GND 3Y 001aad117 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aad118 4066 Transparent top view 3E 3Z 2E 4Z 2Y 4Y 2Z 4E 1Z 1E GND(1) 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description 1Y 1 independent input/output 1Z 2 independent output/input 2Z 3 independent output/input 2Y 4 independent input/output 2E 5 enable input (active HIGH) 3E 6 enable input (active HIGH) GND 7 ground (0 V) 3Y 8 independent input/output 3Z 9 independent output/input 4Z 10 independent output/input 4Y 11 independent input/output 4E 12 enable input (active HIGH) 1E 13 enable input (active HIGH) VCC 14 supply voltage |
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