74AUP1G00_2

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 02 — 29 June 2006

2 of 16

Philips Semiconductors

74AUP1G00

Low-power 2-input NAND gate

3.

Ordering information

4.

Marking

5.

Functional diagram

6.

Pinning information

6.1 Pinning

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP1G00GW

−40 °C to +125 °C

TSSOP5

plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

SOT353-1

74AUP1G00GM

−40 °C to +125 °C

XSON6

plastic extremely thin small outline package; no leads;

6 terminals; body 1

× 1.45 × 0.5 mm

SOT886

74AUP1G00GF

−40 °C to +125 °C

XSON6

plastic extremely thin small outline package; no leads;

6 terminals; body 1

× 1 × 0.5 mm

SOT891

Table 2.

Marking

Type number

Marking code

74AUP1G00GW

pA

74AUP1G00GM

pA

74AUP1G00GF

pA

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram

mna097

B

A

Y

2

1

4

mna098

2

4

&

1

mna099

B

A

Y

Fig 4.

Pin configuration SOT353-1

(TSSOP5)

Fig 5.

Pin configuration SOT886

(XSON6)

Fig 6.

Pin configuration SOT891

(XSON6)

74AUP1G00

B

A

GND

Y

001aaf016

1

2

3

5

4

74AUP1G00

A

001aaf017

B

GND

n.c.

Y

Transparent top view

2

3

1

5

4

6

74AUP1G00

A

001aaf018

B

GND

n.c.

Y

Transparent top view

2

3

1

5

4

6