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ST755C 데이터시트(PDF) 8 Page - STMicroelectronics |
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ST755C 데이터시트(HTML) 8 Page - STMicroelectronics |
8 / 16 page Application circuit ST755C 8/16 6 Application circuit To achieve the best performances from switching power supply topology, particular care to layout drawing is needed, in order to minimize EMI and obtain low noise, jitter free operation moreover, it ensures the full device functionality. Layout design proposed on demoboard (see Figure 4.) helps to lower the developing time. Wire lengths must be minimized, filter and by-pass capacitors C1, C2 and C3 must be low ESR type, placed as close possible to the integrated circuit. The 10µH inductor must be chosen built on a core, taking care that saturation current should be higher than the peak LX switch current. See the Peak inductor current vs. load current graph (Figure 6.). (*) R1 and R2 can be omitted for IO<200mA. (**) C6: Very low noise but poor transient and load response speed. (***) C3 (alternative to C6): faster transient and load response. Figure 3. Typical application circuit |
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