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TC74ACT138P 데이터시트(PDF) 1 Page - Toshiba Semiconductor

부품명 TC74ACT138P
상세설명  CMOS Digital Integrated Circuit Silicon Monolithic 3-to-8 Line Decoder
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TC74ACT138P/F/FN/FT
2007-10-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT138P,TC74ACT138F,TC74ACT138FN,TC74ACT138FT
3-to-8 Line Decoder
The TC74ACT138 is an advanced high speed CMOS 3-to-8
LINE DECODER fabricated with silicon gate and double-layer
metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
When the device is enabled, 3 Binary Select inputs (A, B and
C) determine which one of the outputs ( 0
Y - 7
Y ) will go low.
When enable input G1 is held low or either
A
2
G
or
2B
G
is
held high, decoding function is inhibited and all outputs go high.
G1,
A
2
G
, and
2B
G
inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: tpd = 6.0 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 8 μA (max) at Ta = 25°C
• Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50
Ω
transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Pin and function compatible with 74F138
Note:
xxxFN (JEDEC SOP) is not available in
Japan.
TC74ACT138P
TC74ACT138F
TC74ACT138FN
TC74ACT138FT
Weight
DIP16-P-300-2.54A
: 1.00 g (typ.)
SOP16-P-300-1.27A
: 0.18 g (typ.)
SOL16-P-150-1.27
: 0.13 g (typ.)
TSSOP16-P-0044-0.65A
: 0.06 g (typ.)


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