AD8372

Rev. 0 | Page 10 of 16

THEORY OF OPERATION

The AD8372 is a dual differential variable gain amplifier. Each

amplifier consists of a 150 Ω digitally controlled 6 dB attenuator

followed by a 1 dB vernier and a fixed gain transconductance

amplifier.

The differential output on each amplifier consists of a pair of

open-collector transistors. It is recommended that each open-

collector output be biased to +5 V with a high value inductor.

A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an

excellent choice for this component. A 250 Ω resistor should be

placed across the differential outputs to provide a current-to-

voltage conversion and as a source impedance for passive

filtering, post AD8372.

The gain for each side is based on a 250 Ω differential load and

The dependency of the gain on the load is due to the open-

collector output stage that is biased using external chokes. The

inductance of the chokes and the resistance of the load deter-

mine the low frequency pole of the amplifier. The high frequency

pole is set by the parasitic capacitance of the chokes and outputs

in parallel with the output resistance.

The total supply current of 106 mA per side consists of 70 mA

for the combined outputs and about 36 mA through the power

to set the transconductance of the output stage. For optimum

distortion, 106 mA total current per side is recommended,

reference pin and that same common-mode voltage appears on

the inputs. This reference should be decoupled using a 0.1 μF

capacitor. The part can be powered down to less than 2.6 mA by

setting the ENB pin low for the appropriate side.

The noise figure of the AD8372 is 7.8 dB at maximum gain and

increases as the gain is reduced. The increase in noise figure is

equal to the reduction in gain.

The linearity of the part measured at the output is first-order

independent of the gain setting.

Layout considerations should include minimizing capacitance

on the outputs by avoiding ground planes under the chokes, and

equalizing the output line lengths for phase balance.

SINGLE-ENDED AND DIFFERENTIAL SIGNALS

The AD8372 was designed to be used by applying differential

signals to the inputs and using the differential output drive of

the device to drive the next device in the signal chain. The

excellent distortion performance of the AD8372 is due

primarily to the use of differential signaling techniques to

cancel various distortion components in the device. In addition,

all ac characterization was done using differential signal paths.

Using this device with either the input or the output in a single-

ended circuit significantly degrades the overall performance of

the AD8372.

PASSIVE FILTER TECHNIQUES

The AD8372 has a 100 Ω differential input impedance. For

optimal performance, the differential output load should be

250 Ω. When designing passive filters around the AD8372,

these impedances must be taken into account.

DIGITAL GAIN CONTROL

The digital gain control interface consists of four pins: SDI,

SDO, CLK, and LATCH. The interface is active when the

LATCH pin is shifted low. Gain words are written into the

AD8372 via the SDI pin, and read back from the SDO pin. The

first bit clocked into the data input pin determines whether the

interface is in write or read mode. The second bit is a don’t care

bit, while the remaining six bits program the gain. In read

mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB.

The gain can be programmed between −9 dB and 32 dB in 1 dB

steps. Timing details are given in Figure 2 and Figure 3. The

gain code table is given in Table 3.

DRIVING ANALOG-TO-DIGITAL CONVERTERS

The AD8372 was designed with the intention of driving high

speed, high dynamic range ADCs. The circuit in Figure 14

represents a simplified front end of one-half of the AD8372 dual

VGA driving an AD9445 14-bit, 125 MHz analog-to-digital

converter. The input of the AD8372 is driven differentially

using a 1:3 impedance ratio transformer, which also matches

the 150 Ω input resistance to a 50 Ω source. The open-collector

outputs are biased through the 33 μH inductors and are ac-

coupled from the 142 Ω load resistors that, in parallel with the

2 kΩ input resistance of the ADC, provide a 250 Ω load for gain

accuracy. The ADC is ac-coupled from the 142 Ω resistors to

negate a dc affect on the input common-mode voltage of the

AD9445. Including the series 33 Ω resistors improves the

isolation of the AD8372 from the switching currents caused by

the ADC input sample and hold. The AD9445 represents a 2 kΩ

differential load and requires a 2 V p-p signal when VREF = 1 V

for a full-scale output. This circuit provides variable gain,

isolation, and source matching for the AD9445. Using this

circuit with the AD8372 in a gain of 32 dB (maximum gain), an

SFDR performance of 74.5 dBc is achieved at 85 MHz. See

Figure 15.