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M4T28-BR12SH1 데이터시트(PDF) 8 Page - STMicroelectronics |
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M4T28-BR12SH1 데이터시트(HTML) 8 Page - STMicroelectronics |
8 / 28 page Operation modes M48T35AV 8/28 2 Operation modes As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35AV includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T35AV also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 3V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2. Operating modes Note: X = VIH or VIL; VSO = Battery back-up switchover voltage. 2.1 Read mode The M48T35AV is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). Mode VCC E G W DQ0-DQ7 Power Deselect 3.0 to 3.6V VIH X X High Z Standby WRITE VIL XVIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Deselect VSO to VPFD (min) (1) 1. See Table 11 on page 21 for details. XXXHigh Z CMOS standby Deselect ≤ VSO(1) XXXHigh Z Battery back-up mode |
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