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TC4021BP 데이터시트(PDF) 5 Page - Toshiba Semiconductor |
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TC4021BP 데이터시트(HTML) 5 Page - Toshiba Semiconductor |
5 / 10 page TC4021BP/BF/BFN 2007-10-01 5 Dynamic Electrical Characteristics (Ta = 25°C, VSS = 0 V, CL = 50 pF) Test Condition Characteristics Symbol VDD (V) Min Typ. Max Unit Output transition time (low to high) tTLH ⎯ 5 10 15 ⎯ ⎯ ⎯ 80 50 40 200 100 80 ns Output transition time (high to low) tTHL ⎯ 5 10 15 ⎯ ⎯ ⎯ 80 50 40 200 100 80 ns Propagation delay time (CLOCK-Q) tpLH tpHL ⎯ 5 10 15 ⎯ ⎯ ⎯ 150 65 45 320 160 120 ns Propagation delay time ( S P/ -Q) tpLH tpHL ⎯ 5 10 15 ⎯ ⎯ ⎯ 230 90 60 460 180 120 ns Max clock frequency fCL ⎯ 5 10 15 3.0 6.0 8.5 6.5 18.0 24.0 ⎯ ⎯ ⎯ MHz Min clock pulse width tW ⎯ 5 10 15 ⎯ ⎯ ⎯ 80 30 20 180 80 50 ns Max clock rise time Max clock fall time trCL tfCL ⎯ 5 10 15 20.0 2.5 1.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ μs Min set-up time (SI-CLOCK) tSU ⎯ 5 10 15 ⎯ ⎯ ⎯ 40 20 15 120 80 60 ns Min set-up time (PI- S P/ ) tSU ⎯ 5 10 15 ⎯ ⎯ ⎯ 25 15 10 50 30 20 ns Min hold time (SI-CLOCK), (PI- S P/ ) tH ⎯ 5 10 15 ⎯ ⎯ ⎯ 35 20 15 70 40 30 ns Min pulse width ( S P/ -CONTROL) tWH ⎯ 5 10 15 ⎯ ⎯ ⎯ 90 30 10 180 80 50 ns Min removal time ( S P/ -CLOCK) trem ⎯ 5 10 15 ⎯ ⎯ ⎯ 45 20 15 280 140 100 ns Input capacitance CIN ⎯ ⎯ 5 7.5 pF |
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