전자부품 데이터시트 검색엔진 |
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SST29EE010-150-3I-UH 데이터시트(PDF) 11 Page - Silicon Storage Technology, Inc |
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SST29EE010-150-3I-UH 데이터시트(HTML) 11 Page - Silicon Storage Technology, Inc |
11 / 27 page 11 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS 29EE010 29LE/VE010 Symbol Parameter Min Max Min Max Units TWC Write Cycle (erase and program) 10 10 ms TAS Address Setup Time 0 0 ns TAH Address Hold Time 50 70 ns TCS WE# and CE# Setup Time 0 0 ns TCH WE# and CE# Hold Time 0 0 ns TOES OE# High Setup Time 0 0 ns TOEH OE# High Hold Time 0 0 ns TCP CE# Pulse Width 70 120 ns TWP WE# Pulse Width 70 120 ns TDS Data Setup Time 35 50 ns TDH Data Hold Time 0 0 ns TBLC(1) Byte Load Cycle Time 0.05 100 0.05 100 µs TBLCO(1) Byte Load Cycle Time 200 200 µs TIDA Software ID Access and Exit Time 10 10 µs TSCE Software Chip Erase 20 20 ms Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 304 PGM T13.1 |
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