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SM894051C40 데이터시트(PDF) 10 Page - SyncMOS Technologies,Inc |
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SM894051C40 데이터시트(HTML) 10 Page - SyncMOS Technologies,Inc |
10 / 15 page SyncMOS Technologies International, Inc. SM894051 8-Bits Micro-controller With 4KB Flash ROM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. SM894051 V1.4 09 /2006 10 ORL C,bit C = C .OR. bit 2 2 ORL C,/bit C = C .OR. /bit 2 2 MOV C,bit C = bit 2 1 MOV bit,C bit = C 2 2 JC rel Jump if C= 1 2 2 JNC rel Jump if C= 0 2 2 JB bit,rel Jump if bit = 1 3 2 JNB bit,rel Jump if bit = 0 3 2 JBC bit,rel Jump if C = 1 3 2 Jump Instructions ACALL addr11 Call Subroutine only at 2k bytes Address 2 2 LCALL addr16 Call Subroutine in max 64K bytes Address 3 2 RET Return from subroutine 1 2 RETI Return from interrupt 1 2 AJMP addr11 Jump only at 2k bytes Address 2 2 LJMP addr16 Jump to max 64K bytes Address 3 2 SJMP rel Jump on at 256 bytes 2 2 JMP @A+DPTR Jump to A+ DPTR 1 2 JZ rel Jump if A = 0 2 2 JNZ rel Jump if A ≠ 0 2 2 CJNE A, direct,rel Jump if A ≠ < direct > 3 2 CJNZ A, #data,rel Jump if A ≠ < #data > 3 2 CJNZ Rn, #data,rel Jump if Rn ≠ < #data > 3 2 CJNZ @Ri, #data,rel Jump if @Ri ≠ < #data > 3 2 DJNZ Rn,rel Decrement and jump if Rn not zero 2 2 DJNZ direct,rel Decrement and jump if direct not zero 3 2 NOP No Operation 1 1 Limited on Certain Instructions Branching instructions: The certain instructions related to branching or jumping should be restricted. When the programmer execute the branching instructions like AJMP, LJMP, ACALL, LCALL, SJMP etc..., they have responsibility to ensure that the destination branching address don’t be over internal program memory size. SM894051 contain 4K bytes program memory and its location is from 00H to 0FFFH. Data Memory, MOVX-related instructions: SM894051 contains 128 bytes internal data memory, and it doesn’t support external data memory access. Therefore, SM894051 doesn’t include MOVX instructions. Limited on down mode wake-up SM894051 has two ways to wake-up power down mode. One of them is hardware reset. The other one is that using external interrupt (#INT0, #INT1) to wake-up power down mode and the external interrupt must be set for level trigger. I/O Pin Configuration Port 1: The ports P1.2 to P1.7 have internal pull-up resistor. The ports P1.0 to P1.1 are open-drain configuration, so they require external pull-up resistor to pull low. And P1.0 and P1.1 also used as the positive input (AIN0) and the negative input (AIN1) of the on chip analog comparator. As long as the voltage level of P1.0 is greater than P1.1, the output voltage level of the on-chip analog comparator is “1 “. And this result will be stored in the bit 6 of the port 3 SFR. Port 3: The Port 3 are 7-bits bi-directional I/O pins which include P3.0 to P3.5 and P3.7. The P3.6 doesn't be used as general purpose I/O pin, and the output pin of the on-chip analog comparator connects to the P3.6 which is hard-wired as an input. |
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