1

FEATURES

DRY PACKAGE

(TOP VIEW)

GND

V

CC

B

5

4

2

3

A

Y

1

YZP PACKAGE

(BOTTOMVIEW)

PR

EV

IE

W

6

NC

YFP PACKAGE

(BOTTOMVIEW)

PR

EVIE

W

6

NC

DESCRIPTION/ORDERING INFORMATION

SN74AUP1G08

LOW-POWER SINGLE 2-INPUT POSITIVE-AND GATE

SCES502G – NOVEMBER 2003 – REVISED OCTOBER 2007

www.ti.com

2

• Available in the Texas Instruments NanoFree™

• Optimized for 3.3-V Operation

Package

• 3.6-V I/O Tolerant to Support Mixed-Mode

• Low Static-Power Consumption (I

Signal Operation

Maximum)

• t

• Low Dynamic-Power Consumption

• Suitable for Point-to-Point Applications

• Latch-Up Performance Exceeds 100 mA Per

• Low Input Capacitance (C

JESD 78, Class II

• Low Noise – Overshoot and Undershoot

• ESD Performance Tested Per JESD 22

–

2000-V Human-Body Model

• I

(A114-B, Class II)

Operation

–

200-V Machine Model (A115-A)

• Schmitt-Trigger Action Allows Slow Input

–

1000-V Charged-Device Model (C101)

Transition and Better Switching Noise

• ESD Protection Exceeds ±5000 V With

Human-Body Model

3.3 V)

• Wide Operating V

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal

integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

NanoFree is a trademark of Texas Instruments.

UNLESS

OTHERWISE

NOTED

this

document

contains

Copyright © 2003–2007, Texas Instruments Incorporated

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.