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CDCU877BZQLR 데이터시트(PDF) 7 Page - Seme LAB |
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CDCU877BZQLR 데이터시트(HTML) 7 Page - Seme LAB |
7 / 17 page www.ti.com Switching Characteristics CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS801B – JUNE 2005 – REVISED JULY 2007 over recommended operating free-air temperature range (unless otherwise noted) (see (1)) AV DD, VDD = 1.8 V ± 0.1 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ten Enable time, OE to any Y/Y See Figure 11 8 ns tdis Disable time, OE to any Y/Y See Figure 11 8 ns 160 MHz to 200 MHz, see Figure 4 0 ±40 tjit(cc+) Cycle-to-cycle period jitter(2) 200 MHz to 270 MHz, see Figure 4 0 ±35 ps tjit(cc-) 270 MHz to 340 MHz, see Figure 4 0 ±30 t(ω) Static phase offset time(3) See Figure 5 -50 50 ps t(ω)dyn Dynamic phase offset time See Figure 10 -15 15 ps tsk(o) Output clock skew See Figure 6 25 ps 160 MHz to 200 MHz, see Figure 7 -30 30 tjit(per) Period jitter (4)(2) ps 201 MHz to 340 MHz, see Figure 7 -20 20 160 MHz to 190 MHz, see Figure 8 ±90 tjit(hper) Half-period jitter (4) (2) 190 MHz to 250 MHz, see Figure 8 ±60 ps 250 MHz to 340 MHz, see Figure 8 ±40 Slew rate, OE See Figure 9 0.5 SR Input clock slew rate See Figure 9 1 2.5 4 V/ns Output clock slew rate(5)(6) (no load) See Figure 9 and Figure 13 1.5 2.5 3 (VDDQ/2) - (VDDQ/2) + VOX Output differential-pair cross voltage (7) See Figure 2 V 0.1 0.1 SSC modulation frequency 30 33 kHz SSC clock input frequency deviation 0% -0.5% PLL loop bandwidth 2 MHz (1) There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. (2) This parameter is specifieded by design and characterization. (3) Phase static offset time does not include jitter. (4) Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. (5) The output slew rate is determined from the IBIS model with a 120- Ω load only. (6) To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. (7) Output differential-pair cross voltage specified at the DRAM clock input or the test load. 7 Submit Documentation Feedback |
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