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ISL29010IROZ-EVALZ 데이터시트(PDF) 5 Page - Intersil Corporation |
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ISL29010IROZ-EVALZ 데이터시트(HTML) 5 Page - Intersil Corporation |
5 / 14 page 5 FN6414.0 February 13, 2008 Register Set There are eight registers that are available in the ISL29010. Table 1 summarizes the available registers and their functions. Command Register 00(hex) The Read/Write command register has five functions: 1. Enable; Bit 7.This function either resets the ADC or enables the ADC in normal operation. A logic 0 disables ADC to reset-mode. A logic 1 enables ADC to normal operation. 2. ADCPD; Bit 6. This function puts the device in a power-down mode. A logic 0 puts the device in normal operation. A logic 1 powers down the device. 3. Timing Mode; Bit 5. This function determines whether the integration time is done internally or externally. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fOSC), and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between three consecutive external-sync sync_I2C pulses commands. 4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and Bit 2 to 1 and 0 enables ADC to give light count DATA output. * n = 4, 8, 12,16 depending on the number of clock cycles function. 5. Width; Bits 1 and 0. This function determines the number of clock cycles per conversion. Changing the number of clock cycles does more than just change the resolution of the device. It also changes the integration time, which is the period the device’s analog-to-digital (A/D) converter samples the photodiode current signal for a lux measurement. TABLE 1. REGISTER SET ADDR REG NAME BIT 7 6 5 4 3 2 1 0 DEFAULT 00h COMMAND ADCE ADCPD TIMM 0 ADCM1 ADCM0 RES1 RES0 00h 01h CONTROL 0 0 0 0 GAIN1 GAIN0 0 0 00h 04h LSB SENSOR S7 S6 S5 S4 S3 S2 S1 S0 00h 05h MSB SENSOR S15 S14 S13 S12 S11 S10 S9 S8 00h 06h LSB TIMER T7 T6 T5 T4 T3 T2 T1 T0 00h 07h MSB TIMER T15 T14 T13 T12 T11 T10 T9 T8 00h TABLE 2. WRITE ONLY REGISTERS ADDRESS REGISTER NAME FUNCTIONS/DESCRIPTION b1xxx_xxxx sync_I2C Writing a logic 1 to this address bit ends the current ADC-integration and starts another. Used only with External Timing Mode. bx1xx_xxxx clar_int Writing a logic 1 to this address bit clears the interrupt. TABLE 3. ENABLE BIT 7 OPERATION 0 Disable ADC-core to reset-mode (default) 1 Enable ADC-core to normal operation TABLE 4. ADCPD BIT 6 OPERATION 0 Normal operation (default) 1 Power Down TABLE 5. TIMING MODE BIT 5 OPERATION 0 Internal Timing Mode. Integration time is internally timed determined by fOSC, REXT, and number of clock cycles. 1 External Timing Mode. Integration time is externally timed by the I2C host. TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3 BITS 3:2 MODE 0:0 Disable ADC 0:1 Disable ADC 1:0 Light count DATA output in signed (n - 1) bit * 1:1 No operation. TABLE 7. WIDTH BITS 1:0 NUMBER OF CLOCK CYCLES 0:0 216 = 65,536 0:1 212 = 4,096 1:0 28 = 256 1:1 24 = 16 ISL29010 |
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