AD1934YSTZ-RL datasheet(6/28 Pages) AD

부품명	AD1934YSTZ-RL

상세설명	8-Channel DAC with PLL, 192 kHz, 24 Bits

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AD1934

Rev. 0 | Page 6 of 28

DIGITAL FILTERS

Table 6.

Parameter

Mode

Factor

Min

Typ

Max

Unit

DAC INTERPOLATION FILTER

Pass Band

48 kHz mode, typ @ 48 kHz

0.4535 fS

22

kHz

96 kHz mode, typ @ 96 kHz

0.3646 fS

35

kHz

192 kHz mode, typ @ 192 kHz

0.3646 fS

70

kHz

Pass-Band Ripple

48 kHz mode, typ @ 48 kHz

±0.01

dB

96 kHz mode, typ @ 96 kHz

±0.05

dB

192 kHz mode, typ @ 192 kHz

±0.1

dB

Transition Band

48 kHz mode, typ @ 48 kHz

0.5 fS

24

kHz

96 kHz mode, typ @ 96 kHz

0.5 fS

48

kHz

192 kHz mode, typ @ 192 kHz

0.5 fS

96

kHz

Stop Band

48 kHz mode, typ @ 48 kHz

0.5465 fS

26

kHz

96 kHz mode, typ @ 96 kHz

0.6354 fS

61

kHz

192 kHz mode, typ @ 192 kHz

0.6354 fS

122

kHz

Stop-Band Attenuation

48 kHz mode, typ @ 48 kHz

70

dB

96 kHz mode, typ @ 96 kHz

70

dB

192 kHz mode, typ @ 192 kHz

70

dB

Group Delay

48 kHz mode, typ @ 48 kHz

25/fS

521

μs

96 kHz mode, typ @ 96 kHz

11/fS

115

μs

192 kHz mode, typ @ 192 kHz

8/fS

42

μs

TIMING SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter

Condition

Comments

Min

Max

Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH

MCLK duty cycle

DAC clock source = PLL clock @ 256 fS, 384 fS,

512 fS, 768 fS

40

60

%

tMH

DAC clock source = direct MCLK @ 512 fS

(bypass on-chip PLL)

40

60

%

fMCLK

MCLK frequency

PLL mode, 256 fS reference

6.9

13.8

MHz

fMCLK

Direct 512 fS mode

27.6

MHz

tPDR

RST low

15

ns

tPDRR

RST recovery

Reset to active output

4096

tMCLK

PLL

Lock Time

MCLK and LRCLK input

10

ms

256 fS VCO Clock, Output Duty Cycle

MCLKO Pin

40

60

%

SPI PORT

See Figure 9

tCCH

CCLK high

35

ns

tCCL

CCLK low

35

ns

fCCLK

CCLK frequency

fCCLK = 1/tCCP, only tCCP shown in Figure 9

10

MHz

tCDS

CDATA setup

To CCLK rising

10

ns

tCDH

CDATA hold

From CCLK rising

10

ns

tCLS

CLATCH setup

To CCLK rising

10

ns

tCLH

CLATCH hold

From CCLK falling

10

ns

tCLHIGH

CLATCH high

Not shown in Figure 9

10

ns

tCOE

COUT enable

From CCLK falling

30

ns

tCOD

COUT delay

From CCLK falling

30

ns

tCOH

COUT hold

From CCLK falling, not shown in Figure 9

30

ns

tCOTS

COUT tri-state

From CCLK falling

30

ns

유사한 부품 번호 - AD1934YSTZ-RL

제조업체	부품명	데이터시트	상세설명
Analog Devices	AD1934YSTZ-RL	575Kb / 28P	8-Channel DAC

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AD1934YSTZ-RL 데이터시트(PDF) 6 Page - Analog Devices

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