전자부품 데이터시트 검색엔진 |
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M25P10 데이터시트(PDF) 6 Page - STMicroelectronics |
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M25P10 데이터시트(HTML) 6 Page - STMicroelectronics |
6 / 21 page M25P10 6/21 operation, a one-byte instruction code must be sent to the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the device must have been previously selected (S = low). Table 6 shows the available instruction set. At Power-up and Power-down, the device must not be selected (that is the S input must follow the voltage applied on the VCC pin) until the supply voltage reaches the correct VCC values which are VCC(min) at Power-up and VSS at Power-down (a simple pull-up resistor on S insures safe and proper power up and down phases). Read Data Byte(s) (READ) The device is first selected by putting S low. The Read instruction byte is followed by a three bytes address (A23-A0), each bit being latched-in during the rising edge of the clock (C). Then the data stored in the memory at the selected byte address is shifted out on the Q output pin, each bit being shifted out during the falling edge of the clock (C). The first byte addressed can be any byte within a page. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can therefore be read with a single Read instruction. When the highest address is reached, the address counter rolls over to 000000h allowing the read cycle to be continued indefinitely. The Read operation is terminated by deselecting the chip. The chip can be deselected at any time during data output. Any read attempt during an Erase, Program or Write Status Register cycle will be rejected and will deselect the chip without having any effects on the ongoing operation. The timing sequence is shown in Figure 11. Page Program (PP) Prior to any Page Program attempt, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows the execution of any further Page Program instruction. The Page Program instruction is entered by driving the Chip select input (S) low, followed by the instruction byte, 3 address bytes and at least 1 data byte on Data In input (D). If the least significant address bits differ from [A6- A0]=000.0000, all transmitted data exceeding the addressed page boundary will roll over and will be programmed from address [A6-A0]=000.0000 of this same page. The Chip Select input (S) must be driven low for the entire duration of the sequence. Figure 7. WREN: Set Write Enable Latch Sequence C D AI02281B S Q 2 1 34567 HIGH IMPEDANCE 0 INSTRUCTION Table 6. Instruction Set Instruc tion Description Instruction Format WREN Set Write Enable Latch 0000 0110 WRDI Reset Write Enable Latch 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read Data from Memory Array 0000 0011 PP Program up to 128 Data bytes to Memory Array 0000 0010 SE Sector Erase (set to FFh) one sector of Memory Array 1101 1000 BE Bulk Erase (set to FFh) whole of Memory Array 1100 0111 DP Enter Deep Power-down mode 1011 1001 RES Release from Deep Power- down mode, and Read Electronic Signature 1010 1011 |
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