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SMS064FFA5E 데이터시트(PDF) 15 Page - Numonyx B.V |
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15 / 61 page SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface 15/61 3.1 Secure digital memory card bus topology The Secure Digital Memory Card system defines two alternative communications protocols: SD and SPI that correspond to two operating modes. Either mode can be selected in the application, mode selection is transparent to the host. The host automatically detects the operating mode of the card by issuing the Reset command (refer to Section 7.2.1: Mode Selection) and will expect all further communications to use the same mode. Therefore, applications that use only one communication mode do not have to be aware of the other. The SD bus includes the following signals: ● CLK: Host to card clock signal ● CMD: Bi-directional Command/Response signal ● DAT0 - DAT3: 4 Bi-directional data signals. ● VDD, VSS1, VSS2: Power and ground signals. The SD Memory Card bus has a synchronous star topology (refer to Figure 4: Secure Digital Memory Card system bus topology) with a single master (the application) and multiple slaves (the cards). The Clock, power and ground signals are common to all cards. The command (CMD) and data (DAT0 - DAT3) signals are dedicated to the cards, they provide continuous point-to-point connection to all the cards. During the initialization process, commands are sent to each card individually, allowing the application to detect the cards and assign logical addresses to the physical slots. Data is always sent (received) to (from) each card individually. However, in order to simplify the handling of the card stack, after the initialization process, all commands may be sent concurrently to all cards. Addressing information is provided in the command packet. The SD bus allows dynamic configuration of the number of data lines. After power-up the SD Memory Card defaults to using only DAT0 for data transfer. After initialization the host can change the bus width (number of active data lines). This feature is an easy trade off between hardware cost and system performance. |
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