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SN74CBTLV16210DLR 데이터시트(PDF) 2 Page - Texas Instruments |
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SN74CBTLV16210DLR 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 11 page SN74CBTLV16210 LOW VOLTAGE 20BIT FET BUS SWITCH SCDS042J − DECEMBER 1997 − REVISED JULY 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) 1A1 SW 1B1 1A10 1OE SW 1B10 2A1 SW 2B1 2A10 2OE SW 2B10 2 12 48 13 24 47 46 36 35 25 simplified schematic, each FET switch A (OE) B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC −0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (see Note 1) −0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous channel current 128 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0) −50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DGV package 58 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DL package 63 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg −65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. |
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