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M29F800AT 데이터시트(PDF) 4 Page - STMicroelectronics |
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M29F800AT 데이터시트(HTML) 4 Page - STMicroelectronics |
4 / 21 page M29F800AT, M29F800AB 4/21 Table 3A. M29F800AT Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16) 16 FC000h-FFFFF h 7E000h-7FFFFh 8 FA000h-FBFFFh 7D000h-7DFFFh 8 F8000h-F9FFFh 7C000h-7CFFFh 32 F0000h-F7FFFh 78000h-7BFFFh 64 E0000h-EFFFF h 70000h-77FFFh 64 D0000h-DFFFFh 68000h-6FFFFh 64 C0000h-CFFFFh 60000h-67FFFh 64 B0000h-BFFFF h 58000h-5FFFFh 64 A0000h-AFFFF h 50000h-57FFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 64 00000h-0FFFFh 00000h-07FFFh Table 3B. M29F800AB Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16) 64 F0000h-FFFFF h 78000h-7FFFFh 64 E0000h-EFFFFh 70000h-77FFFh 64 D0000h-DFFFF h 68000h-6FFFFh 64 C0000h-CFFFF h 60000h-67FFFh 64 B0000h-BFFFFh 58000h-5FFFFh 64 A0000h-AFFFFh 50000h-57FFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 32 08000h-0FFFFh 04000h-07FFFh 8 06000h-07FFFh 03000h-03FFFh 8 04000h-05FFFh 02000h-02FFFh 16 00000h-03FFFh 00000h-01FFFh Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Reset/Block Temporary Unprotect (RP). The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 14 and Figure 10, Reset/Temporary Unprotect AC Characteris- tics. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch be- tween the 8-bit and 16-bit Bus modes of the mem- ory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode. |
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