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M40Z300MQ 데이터시트(PDF) 5 Page - STMicroelectronics |
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5 / 16 page 5/16 M40Z300, M40Z300W POWER-ON RESET OUTPUT All microprocessors have a reset input which forc- es them to a known state when starting. The M40Z300/W has a reset output (RST) pin which is guaranteed to be low within tWPT of VPFD (See Ta- ble 7). This signal is an open drain configuration. An appropriate pull-up resistor should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when VCC equals VSS. Once VCC exceeds the power failure detect volt- age VPFD, an internal timer keeps RST low for tREC to allow the power supply to stabilize. TWO TO FOUR DECODE The M40Z300/W includes a 2 input (A, B) decoder which allows the control of up to 4 independent SRAMs. The Truth Table for these inputs is shown in Table 3. Figure 4. Hardware Hookup AI02395 VCC E E1CON VSS VOUT VCC CMOS SRAM 3.0V, 3.3V or 5V THS A 0.1 µF 0.1 µF M40Z300 M40Z300W Threshold E B E2CON E3CON E4CON RST BL E VCC CMOS SRAM 0.1 µF E VCC CMOS SRAM 0.1 µF E VCC CMOS SRAM 0.1 µF To Microprocessor To Battery Monitor Circuit |
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