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AD8177 데이터시트(PDF) 5 Page - Analog Devices |
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AD8177 데이터시트(HTML) 5 Page - Analog Devices |
5 / 40 page AD8177 Rev. 0 | Page 5 of 40 TIMING CHARACTERISTICS (SERIAL MODE) Table 2. Limit Parameter Symbol Min Typ Max Unit Serial Data Setup Time t1 40 ns CLK Pulse Width t2 60 ns Serial Data Hold Time t3 50 ns CLK Pulse Separation t4 140 ns CLK to UPDATE Delay t5 10 ns UPDATE Pulse Width t6 90 ns CLK to SEROUT Valid t7 120 ns Propagation Delay, UPDATE to Switch On 80 ns Data Load Time, CLK = 5 MHz, Serial Mode 9 μs RST Time 140 200 ns LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE t2 t4 1 0 CLK 1 0 1 0 SERIN OUT4 (D4) t1 t3 OUT4 (D3) OUT0 (D0) 1 = LATCHED 0 = TRANSPARENT UPDATE TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t5 t7 SEROUT t6 Figure 2. Timing Diagram, Serial Mode Table 3. Logic Levels, VDD = 3.3 V VIH VIL VOH VOL IIH IIL IOH IOL SER/PAR, CLK, SERIN, UPDATE SER/PAR, CLK, SERIN, UPDATE SEROUT SEROUT SER/PAR, CLK, SERIN, UPDATE SER/PAR, CLK, SERIN, UPDATE SEROUT SEROUT 2.0 V min 0.6 V max 2.8 V min 0.4 V max 20 μA max –20 μA max –1 mA min 1 mA min Table 4. H and V Logic Levels, VDD = 3.3 V VOH VOL IOH IOL 2.7 V min 0.5 V max –3 mA max 3 mA max Table 5. RST Logic Levels, VDD = 3.3 V VIH VIL IIH IIL 2.0 V min 0.6 V max −60 μA max −120 μA max Table 6. CS Logic Levels, VDD = 3.3 V VOH VOL IIH IOL 2.0 V min 0.6 V max 100 μA max 40 μA max |
유사한 부품 번호 - AD8177 |
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