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SN74ABT273PWRE4 데이터시트(PDF) 4 Page - Texas Instruments |
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SN74ABT273PWRE4 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 18 page SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C SN54ABT273 SN74ABT273 UNIT MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 150 0 150 0 150 MHz t Pulse duration CLK high or low 3.3 3.3 3.3 ns tw Pulse duration CLR low 3.3 3.3 3.3 ns ↑ Data high 2 2 2 tsu Setup time before CLK ↑ Data low 2.5 2.5 2.5 ns CLR high 2 2 2 th Hold time after CLK ↑ Data high or low 1.2† 1.4† 1.2† ns † This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN54ABT273 UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 150 150 MHz tPLH CLK Q 2.5 6 2.5 7 ns tPHL CLK Q 3.3 6.8 3.3 7.5 ns tPHL CLR Q 2.5 7.5† 2.5 8.2 ns † This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN74ABT273 UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX fmax 150 150 MHz tPLH CLK Q 2.5 6 2.5 6.5 ns tPHL CLK Q 3.3 6.8 3.3 7.3 ns tPHL CLR Q 2.5 6.7† 2.5 7.4† ns † This data sheet limit may vary among suppliers. |
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