Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
DSDIVORIDE
reserved
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Type
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
DSOSCSRC
reserved
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:29
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
0x0F
R/W
DSDIVORIDE
28:23
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
22:7
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
Description
Name
Value
No override to the oscillator clock source is done
NOORIDE
0x0
Use internal 12 MHz oscillator as source
IOSC
0x1
Use 30 kHz internal oscillator
30kHz
0x3
Use 32 kHz external oscillator
32kHz
0x7
0x0
R/W
DSOSCSRC
6:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
3:0
77
September 02, 2007
Preliminary
LM3S8730 Microcontroller