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LM3S8730-IQN20-B0 데이터시트(PDF) 81 Page - List of Unclassifed Manufacturers

부품명 LM3S8730-IQN20-B0
상세설명  Microcontroller
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Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0100.30DF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
CAN0
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
JTAG
SWD
SWO
WDT
PLL
reserved
HIB
MPU
reserved
MINSYSDIV
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
1
1
1
1
1
0
1
1
0
0
0
0
1
1
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:25
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
1
RO
CAN0
24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
23:16
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Description
Value
Specifies a 50-MHz CPU clock with a PLL divider of 4.
0x3
0x3
RO
MINSYSDIV
15:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
11:8
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
1
RO
MPU
7
Hibernation Module Present
When set, indicates that the Hibernation module is present.
1
RO
HIB
6
81
September 02, 2007
Preliminary
LM3S8730 Microcontroller


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