전자부품 데이터시트 검색엔진 |
|
AD7492BR-5 데이터시트(PDF) 11 Page - Analog Devices |
|
AD7492BR-5 데이터시트(HTML) 11 Page - Analog Devices |
11 / 16 page REV. 0 AD7492 –11– t2 tCONVERT t3 t4 t8 t5 t6 t7 t9 t10 BUSY CS RD DBx CONVST Figure 9. Parallel Port Timing t2 tCONVERT t9 CONVST BUSY DBx DATA N DATA N+1 Figure 10. Parallel Port Timing with CS and RD Tied Low this mode a new conversion should not be initiated until 140 ns after BUSY goes low. This acquisition time allows the track/hold circuit to accurately acquire the input signal. As mentioned earlier, a read should not be done during a conversion. This mode facilitates the fastest throughput times for the AD7492. Mode 2 (Partial or Full Sleep Mode) Figure 11 shows AD7492 in Mode 2 operation where the ADC goes into either partial or full sleep mode after conversion. The CONVST line is brought low to initiate a conversion and remains low until after the end of conversion. If CONVST goes high and low again while BUSY is high, the conversion is restarted. Once the BUSY line goes from a high to a low, the CONVST line has its status checked and, if low, the part enters a sleep mode. The type of sleep mode the AD7492 enters depends on what ever way the PS/ FS pin is hardwired. If the PS/FS pin is tied high, the AD7492 will enter partial sleep mode. If the PS/ FS pin is tied low, the AD7492 will enter full sleep mode. The device wakes up again on the rising edge of the CONVST signal. From partial sleep the AD7492 is capable of starting conversions typically 1 µs after the rising edge of CONVST. The CONVST line can go from a high to a low during the wake-up time, but the conversion will still not be initiated until after 1 µs. We recommend that conversion should not be initiated until at least 20 µs of the wake-up time has elapsed. This will ensure that the AD7492 has stabilized to within 0.5 LSB of the analog input value. After 1 µs, the AD7492 will have only stabilized to within approximately 3 LSB of the input value. From full sleep this wake- up time is typically 500 µs. In all cases the BUSY line will only go high once CONVST goes low. Superior power performance can be achieved in these modes of operation by waking up the AD7492 only to carry out a conversion. The optimum power performance is obtained when using full sleep mode as the ADC comparator, Reference buffer and Reference circuit is powered down. While in partial sleep mode, only the ADC comparator is powered down and the reference buffer is put into a low power mode. The 100 nF capacitor on the REF OUT pin is kept charged up by the reference buffer in partial sleep mode while in full sleep mode this capacitor slowly discharges. This explains why the wake-up time is shorter in partial sleep mode. In both sleep modes the clock oscillator circuit is powered down. CONVST BUSY CS RD DBx tWAKEUP tCONVERT Figure 11. Mode 2 Operation |
유사한 부품 번호 - AD7492BR-5 |
|
유사한 설명 - AD7492BR-5 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |