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74LCX646TTR 데이터시트(PDF) 1 Page - STMicroelectronics |
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1 / 16 page 1/16 September 2004 s 5V TOLERANT INPUTS AND OUTPUTS s HIGH SPEED: tPD = 7.0 ns (MAX.) at VCC = 3V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 646 s LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX646 is a low voltage CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. This device consists of bus transceiver circuits with 3 state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into register on the low to high transition of the appropriate clock pin (Clock AB or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode 74LCX646 LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE) Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LCX646RM13TR TSSOP 74LCX646TTR TSSOP SOP Rev. 6 |
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