전자부품 데이터시트 검색엔진 |
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74LVQ245 데이터시트(PDF) 1 Page - STMicroelectronics |
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74LVQ245 데이터시트(HTML) 1 Page - STMicroelectronics |
1 / 12 page 1/12 July 2004 s HIGH SPEED: tPD = 5.7 ns (TYP.) at VCC = 3.3 V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC = 5 µA (MAX.) at TA=25°C s LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ245 is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. All floating bus terminals during High Impedance State must be held HIGH or LOW. 74LVQ245 LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER WITH (3-STATE) Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LVQ245MTR TSSOP 74LVQ245TTR TSSOP SOP Rev. 5 |
유사한 부품 번호 - 74LVQ245_04 |
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유사한 설명 - 74LVQ245_04 |
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