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LFX1200B-3FN256I 데이터시트(PDF) 4 Page - Lattice Semiconductor |
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LFX1200B-3FN256I 데이터시트(HTML) 4 Page - Lattice Semiconductor |
4 / 115 page Lattice Semiconductor ispXPGA Family Data Sheet 4 Figure 1. ispXPGA Block Diagram Programmable Function Unit The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen- erator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of the function capabilities of the PFU. There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con- trol logic from which six control signals are derived for the PFU. Table 3. Function Capability of ispXPGA PFU Function Capability Look-up table LUT-4, LUT-5, LUT-6 Wide logic functions Up to 20 input logic functions Multiplexing 2:1, 4:1, 8:1 Arithmetic logic Dedicated carry chain and booth multiplication logic Single-port RAM 16X1, 16X2, 16X4, 32X1, 32X2, 64X1 Double-port RAM 16X1, 16X2, 32X1 Shift register 8-bit shift registers (up to 32-bit shift capability) PFU PIC sysHSI Block sysCLOCK PLL sysIO Buffer sysMEM Block |
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