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LC51024MV-75FN256C 데이터시트(PDF) 3 Page - Lattice Semiconductor |
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LC51024MV-75FN256C 데이터시트(HTML) 3 Page - Lattice Semiconductor |
3 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 3 5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs are provided to allow the synthesis of new clocks and control of clock skews. Multi-Function Block (MFB) Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides a flexible approach to implementing logic and memory that allows the designer to achieve the mix of functions that are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are: • SuperWIDE Logic Mode • True Dual-port SRAM Mode • Pseudo Dual-port SRAM Mode • Single-port SRAM Mode • FIFO Mode • Ternary CAM Mode The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multi- function array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs data along with certain control functions to the macrocells. Output signals can be routed internally for use else- where in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various configurations are described in more detail in the following sections. Figure 2. MFB Block Diagram To Routing PTOE Sharing Cascade Out Multifunction Array True Dual Port RAM (8,192 bit) Pseudo Dual Port RAM (16,384 bit) Single Port RAM (16,384 bit) FIFO (16,384 bit) Ternary CAM (128*48) Logic (68 Input * 164 Product Term Array, 32 MC) |
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