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STP85NF3LL 데이터시트(PDF) 1 Page - STMicroelectronics |
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1 / 9 page 1/9 PRELIMINARY DATA March 2001 STP85NF3LL STB85NF3LL-1 N-CHANNEL 30V - 0.006 Ω - 85A TO-220/I2PAK LOW GATE CHARGE STripFET™ POWER MOSFET s TYPICAL RDS(on) = 0.0075 Ω (@4.5V) s OPTIMAL RDS(ON) x Qg TRADE-OFF @4.5V s CONDUCTION LOSSES REDUCED s SWITCHING LOSSES REDUCED DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronics unique “ Single Feature Size” strip-based process. The re- sulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high effi- ciency are of paramount importance. APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS (q) Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STP85NF3LL STB85NF3LL-1 30 V 30 V < 0.008 Ω < 0.008 Ω 85 A 85 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 30 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 30 V VGS Gate- source Voltage ± 15 V ID Drain Current (continuos) at TC = 25°C 85 A ID Drain Current (continuos) at TC = 100°C 60 A IDM (q) Drain Current (pulsed) 340 A PTOT Total Dissipation at TC = 25°C 110 W Derating Factor 0.73 W/°C Tstg Storage Temperature –65 to 175 °C Tj Max. Operating Junction Temperature 175 °C TO-220 1 2 3 1 2 3 I2PAK INTERNAL SCHEMATIC DIAGRAM |
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