STPCE1EEBC datasheet(8/87 Pages) STMICROELECTRONICS

부품명	STPCE1EEBC

상세설명	X86 Core General Purpose PC Compatible System - on - Chip

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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GENERAL DESCRIPTION

8/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1.4. CLOCK TREE

The STPC Elite integrates many features and

generates all its clocks from a single 14MHz

oscillator. This results in multiple clock domains as

described in Figure 1-2.

The speed of the PLLs is either fixed (DEVCLK),

either programmable by strap option (HCLK)

either

programmable

by

software

(GPCLK,

MCLK). When in synchronized mode, MCLK

speed is fixed to HCLKO speed and HCLKI is

generated from MCLKI.

Figure 1-2. STPC Elite clock architecture

IPC

SDRAM controller

North Bridge

14.31818 MHz

XTALO

XTALI

OSC14M

ISACLK

1/4

GPCLK

PLL

(14MHz)

1/2

HCLK

PLL

PCICLKI

PCICLKO

South Bridge

1/2

1/3

HCLK

MCLK

PLL

MCLKI

MCLKO

CPU

x1

x2

Local Bus

Host

ISA

HCLKI

HCLKO

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STPCE1EEBC 데이터시트(PDF) 8 Page - STMicroelectronics

STPCE1EEBC 데이터시트(HTML) 8 Page - STMicroelectronics

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