전자부품 데이터시트 검색엔진 |
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FIN12AC 데이터시트(PDF) 7 Page - Fairchild Semiconductor |
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FIN12AC 데이터시트(HTML) 7 Page - Fairchild Semiconductor |
7 / 21 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.2 7 LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half VDDP. The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source / sink current of 2mA at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH, the bi-directional LVCMOS I/Os are in HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Figure 3. LVCMOS I/O Application Mode Diagrams Modes 1, 2, 3: Unidirectional Data Transfer Figure 4. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 4. shows basic operation when a pair of µSerDes is configured in an unidirectional operation mode. Master Operation: 1. During power-up, the device is configured as a serializer based on the value of the DIRI signal. 2. The device accepts CKREF_M word clock and gen- erates a bit clock, which is sent to the slave device through the CKSO port. 3. The device receives parallel data on the rising edge of STROBE_M. 4. The device generates and transmits serialized data on the DS signals, which is source synchronous with CKSO. 5. The device generates an embedded word clock for each strobe signal. Slave Operation: 1. The device is configured as a deserializer at power- up based on the value of the DIRI signal. 2. The device accepts the bit clock on CKSI. 3. The device deserializes the DS data stream using the CKSI input clock. 4. The device writes parallel data onto the DP_S port and generates the CKP_S only when a valid data word occurs. From Deserializer To Serializer From Control DP[n] + – + – + – + – CKREF_M CKSO CKSI CKP_S DP[1:12]_S Serializer Control BIT CK Gen. PLL Master Device Operating as a Serializer DIR = “1” Slave Device Operating as a Deserializer DIR = “0” Deserializer Control Work CK Gen Serializer Deserializer DS STROBE_M DP[1:12]_M |
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