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HD64336032G 데이터시트(PDF) 77 Page - Renesas Technology Corp |
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HD64336032G 데이터시트(HTML) 77 Page - Renesas Technology Corp |
77 / 592 page Section 2 CPU Rev. 4.00 Mar. 15, 2006 Page 45 of 556 REJ09B0026-0400 • BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0). • After executing BSET instruction MOV.B @RAM0, R0L MOV.B R0L, @PDR5 The work area (RAM0) value is written to PDR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 1 RAM0 1 0 0 0 0 0 0 1 (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. • Prior to executing BCLR instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 |
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