CS2300-CP

DS843PP1

3

8.5 Ratio (Address 06h - 09h) .............................................................................................................. 27

8.6 Function Configuration 1 (Address 16h) ........................................................................................ 27

8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 27

8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 27

8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) ........................................................ 27

8.7 Function Configuration 2 (Address 17h) ........................................................................................ 28

8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 28

8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 28

8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 28

8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 28

9. CALCULATING THE USER DEFINED RATIO .................................................................................... 29

9.1 High Resolution 12.20 Format ....................................................................................................... 29

9.2 High Multiplication 20.12 Format ................................................................................................... 29

10. PACKAGE DIMENSIONS .................................................................................................................. 30

THERMAL CHARACTERISTICS ......................................................................................................... 30

11. ORDERING INFORMATION .............................................................................................................. 31

12. REFERENCES .................................................................................................................................... 31

13. REVISION HISTORY .......................................................................................................................... 31

LIST OF FIGURES

Figure 1. Typical Connection Diagram ........................................................................................................ 5

Figure 2. Control Port Timing - I²C Format .................................................................................................. 8

Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9

Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10

Figure 5. Hybrid Analog-Digital PLL .......................................................................................................... 11

Figure 6. External Component Requirements for LCO ............................................................................. 12

Figure 10. Low bandwidth and new clock domain .................................................................................... 14

Figure 11. High bandwidth with CLK_IN domain re-use ........................................................................... 15

Figure 12. Ratio Feature Summary ........................................................................................................... 18

Figure 13. PLL Clock Output Options ....................................................................................................... 19

Figure 14. Auxiliary Output Selection ........................................................................................................ 19

Figure 15. Control Port Timing in SPI Mode ............................................................................................. 21

Figure 16. Control Port Timing, I²C Write .................................................................................................. 22

Figure 17. Control Port Timing, I²C Aborted Write + Read .......................................................................22

LIST OF TABLES

Table 1. PLL Input Clock Range Indicator ................................................................................................ 12

Table 2. Ratio Modifier .............................................................................................................................. 16

Table 3. Automatic Ratio Modifier ............................................................................................................. 16

Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 17

Table 5. Example 12.20 R-Values ............................................................................................................ 29

Table 6. Example 20.12 R-Values ............................................................................................................ 29