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AT89S52

WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-

tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be

serviced in those sections of code that will periodically be executed within the time required to

prevent a WDT reset.

7.2

WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-

down mode, the user does not need to service the WDT. There are two methods of exiting

Power-down mode: by a hardware reset or via a level-activated external interrupt which is

enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,

servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting

Power-down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent

the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until

the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for

the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to

reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether

the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)

as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the

user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter

IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count

upon exit from IDLE.

8.

UART

The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52.

For further information on the UART operation, please click on the document link below:

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

9.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the

AT89C51 and AT89C52. For further information on the timers’ operation, please click on the

document link below:

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF