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ATMEGA128 데이터시트(PDF) 56 Page - ATMEL Corporation

부품명 ATMEGA128
상세설명  8-bit Microcontroller with 128K Bytes In-System Programmable Flash
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제조업체  ATMEL [ATMEL Corporation]
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56
2467R–AVR–06/08
ATmega128
Figure 28. Watchdog Timer
Watchdog Timer
Control Register –
WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits. See “Timed Sequences for Changing the
Configuration of the Watchdog Timer” on page 58.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.
M103C
WDTON
Safety
Level
WDT Initial
State
How to Disable
the WDT
How to
Change
Time-out
Unprogrammed
Unprogrammed
1
Disabled
Timed
sequence
Timed
sequence
Unprogrammed
Programmed
2
Enabled
Always enabled
Timed
sequence
Programmed
Unprogrammed
0
Disabled
Timed
sequence
No
restriction
Programmed
Programmed
2
Enabled
Always enabled
Timed
sequence
WATCHDOG
OSCILLATOR
Bit
765
4321
0
WDCE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
000
0000
0


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