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CDCE18005RGZR 데이터시트(PDF) 7 Page - Texas Instruments |
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CDCE18005RGZR 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 58 page Output Block /1,2,3,4,5 UxP UxN /1 - /8 /2 DigitalPhase Adjust (7 -bits ) PRI_IN SEC_IN SMART_MUX SYNTH Sync Pulse Enable LVDS ClockDividerModule0-4 LVPECL Output MUX Control OutputBufferControl /1-/80 DigitalPhase Adjust(7-bits) SyncPulse (internallygenerated) Enable From Output MUX To Output Buffer CDCE18005 www.ti.com........................................................................................................................................................................................... SCAS863 – NOVEMBER 2008 Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a universal output array as shown. Figure 6. CDCE18005 Output Block (1 of 5) Clock Divider Module 0–4 The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each output. Figure 7. CDCE18005 Output Divider Module (1 of 5) Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s) :CDCE18005 |
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