전자부품 데이터시트 검색엔진 |
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TC7117 데이터시트(PDF) 7 Page - TelCom Semiconductor, Inc |
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TC7117 데이터시트(HTML) 7 Page - TelCom Semiconductor, Inc |
7 / 14 page 3-209 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 Reference Integrate Phase The final phase is reference integrate, or deintegrate. Input low is internally connected to analog common and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. The digital reading displayed is: TC7116 TC7116A TC7117 TC7117A CREF C REF BUFF CREF – RINT V + CAZ AUTO- ZERO VINT 28 35 29 27 33 36 34 10 µA 31 A/Z A/Z INT A/Z & DE (±) 32 30 INT 26 INTEGRATOR V + –3V COMPARATOR TO DIGITAL SECTION DE (+) DE (–) DE (+) DE (–) V + A/Z ANALOG COMMON + V IN + V IN – V CINT VREF + LOW TEMP DRIFT ZENER VREF V – + – + – + + – ANALOG SECTION (All Pin designations refers to 40-Pin Dip) Figure 3 shows the block diagram of the analog section for the TC7116/TC7116A and TC7117/TC7117A. Each measurement cycle is divided into three phases: (1) auto- zero (A-Z), (2) signal integrate (INT), and (3) reference integrate (REF) or deintegrate (DE). Auto-Zero Phase High and low inputs are disconnected from the pins and internally shorted to analog common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system to charge the auto-zero capacitor (CAZ) to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the com- parator is included in the loop, A-Z accuracy is limited only by system noise. The offset referred to the input is less than 10 µV. Signal-Integrate Phase The auto-zero loop is opened, the internal short is removed, and the internal high and low inputs are con- nected to the external pins. The converter then integrates the differential voltages between V + IN and V – IN for a fixed time. This differential voltage can be within a wide com- mon-mode range; 1V of either supply. However, if the input signal has no return with respect to the converter power supply, V – IN can be tied to analog common to establish the correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is determined. Figure 3. Analog Section of TC7116/TC7116A and TC7117/TC7117A 1000 × . VIN VREF Reference The positive reference voltage (V + REF) is referred to analog common. Differential Input This input can accept differential voltages anywhere within the common-mode range of the input amplifier or, specifically, from 1V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86 dB, typical. However, since the integrator also swings with the common-mode voltage, care must be exercised to ensure that the integrator output does not saturate. A worst- case condition would be a large, positive common- mode voltage with a near full-scale negative differential input voltage. The negative-input signal drives the integra- tor positive when most of its swing has been used up by the positive common-mode voltage. For these critical applica- tions, the integrator swing can be reduced to less than the TC7116 TC7116A TC7117 TC7117A 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD |
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