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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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RT3PE3000L-1FG484B 데이터시트(PDF) 16 Page - Actel Corporation |
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RT3PE3000L-1FG484B 데이터시트(HTML) 16 Page - Actel Corporation |
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16 / 144 page  Radiation-Tolerant ProASIC3 FPGAs 2- 4 A d vance v0.1 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6. There are five regions to consider during power-up. RT ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. |
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유사한 설명 - RT3PE3000L-1FG484B |
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