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A3PE3000-1FGG896I 데이터시트(PDF) 63 Page - Actel Corporation

부품명 A3PE3000-1FGG896I
상세설명  ProASIC3E Flash Family FPGAs
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제조업체  ACTEL [Actel Corporation]
홈페이지  http://www.actel.com
Logo ACTEL - Actel Corporation

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ProASIC3E DC and Switching Characteristics
v1.2
2 - 51
Table 2-80 • Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
Measuring Nodes
(from, to)*
tOCLKQ
Clock-to-Q of the Output Data Register
H, DOUT
tOSUD
Data Setup Time for the Output Data Register
F, H
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
G, H
tOHE
Enable Hold Time for the Output Data Register
G, H
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
L, DOUT
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
L, H
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
L, H
tOECLKQ
Clock-to-Q of the Output Enable Register
H, EOUT
tOESUD
Data Setup Time for the Output Enable Register
J, H
tOEHD
Data Hold Time for the Output Enable Register
J, H
tOESUE
Enable Setup Time for the Output Enable Register
K, H
tOEHE
Enable Hold Time for the Output Enable Register
K, H
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
I, EOUT
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
I, H
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
I, H
tICLKQ
Clock-to-Q of the Input Data Register
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tISUE
Enable Setup Time for the Input Data Register
B, A
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
D, E
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
D, A
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
D, A
* See Figure 2-24 on page 2-50 for more information.


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