5

FN6835.0

February 9, 2009

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS

capacitance.

FIGURE 2B. TEST CIRCUIT

FIGURE 2. BREAK-BEFORE-MAKE TIME

50%

90%

0V

0V

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

V

OUT

V

(INPUT)

R

L

R

L

r

ON

+

------------------------

=

SWITCH

INPUT

VIN

Dx

HSDxx

SEL

GND

C

OE

90%

0V

LOGIC

INPUT

SWITCH

OUTPUT

0V

VIN

SEL

Dx

HSD2x

GND

C

OE

HSD1x

C

HSDx

Dx

SEL

GND

40mA

Repeat test for all switches.

OE

ISL54222