Single-Channel

Mode

Dual-Channel

Mode

FIFO

Addressing

External

Address Port

2-D Addressing

Auto TRS

Decode &

Pointer Clear

Empty/Full

Flags

LOGIC Devices Incorporated

www.logicdevices.com

January 23, 2008 LDS-44xx-A

High Performance Memory Product

4

MEMORY

FRAME

Video Memory / FIFO

LF4460

LF4430

LF4415

PRELIMINARY

Operating Modes

Single-Channel FIFO Configuration (MODE = 0xxx) The LF44xx memory can be organized as a single

channel deep FIFO (from 8 to 24bits wide), with independent read and write ports and clocks to allow for

fully independent/asynchronous operation. This mode is ideal for rate matching, frame synchronization, and

image manipulation applications.

Dual Independent FIFOs Configuration (MODE = 11xx) Dual-channel mode is designed for applications

requiring independent control of two FIFOs in one device. Each channel of the LF44xx operates as an

independent FIFO with the exceptions of A) both channels share a common read clock RCLK and B)

memory access using an external address port is not possible. Each channel input, control, or output is

identified by its suffix “0” or “1”. (Ex: D0, WEN0 versus D1, WEN1, etc...)

Buffering/synchronization applications often require sequential FIFO addressing, where the read pointer

chases the write pointer across the memory address space. The first data sample (or pixel) of a frame of

data is generally referenced to address zero in memory. This is implemented by clearing the write pointer

(bringing WCLR0 LOW) on the first sample of each frame of data written into memory. Upon requesting

a frame of data from memory starting with address zero (pixel 0), the read pointer is cleared (by bringing

RCLR0 LOW). The LF4430 write and read address pointers increment automatically through the memory

address space, and memory writes/reads are enabled, when WEN0 and REN0 are LOW respectively.

For applications requiring arbitrary access to memory addresses, a 24bit external address port is provided.

This 24bit address port provides access to the entire memory space on a cycle by cycle basis and can

be used to override the Write or Read sequential FIFO address pointers. The write address is forced to

the value defined by the 24bit external address port by bringing WSET0 LOW (assuming ADSEL is LOW).

The read pointer is forced to the value defined by the 24bit external address port by bringing RSET LOW

(assuming RDWR is HIGH). The external address can be updated each write or read cycle, depending

on which port is being addressed, to enable such applications as image rotation, PIP, region of interest

extraction, etc. Once the write or read address pointer override is to be terminated (bringing WSET0 or

RSET back HIGH), the write or read address pointer resumes sequential increment sequence starting at the

last address overriden by the address port (see Address Control table).

The LF44xx memory can be mapped as a linear address space (sequential FIFO addressing from say 0

to FFFF) or as a 2-D address space (as an image is addressed - using rows and columns). 2-D address

mapping simplifies complex address manipulation requirements that exist in video and image processing. In

order to access the memory using a 2-D address space, the external 24bit address port defines a 12bit row

and column address for writing or reading. See Control Registers 0 and 1.

Timing Reference Signals (TRS) from the incoming video stream are automatically detected and continu-

ously monitored. The field (‘F’) or vertical blanking (‘V’) bits in the TRS sequence can be programmed

to auto-clear the write address pointer to zero. This is useful in synchronization applications by relieving

the designer of routing SYNC signals from the upstream decoder, deserializer, or processor to the FIFO

Write address controls.

If the read and write address pointers collide, the COLLIDE0 flag will be brought HIGH, to alert the

host. The programmable almost-full (PF) and almost-empty (PE) flags provide advance warning of pointer

collisions. They are triggered when the R/W pointers are within user-specified “fullness” or “emptiness”

thresholds. Thresholds are set by the user and can be written into configuration registers (see registers

0D-18), and are defaulted to 1/80th for PE and 79/80th for PF. For example, if the flags are defaulted to the

1/80 and 79/80 thresholds, flag PE0 will go HIGH whenever the read pointer lags behind the write pointer by

less than 1/80 of the memory space, and flag PF0 will go HIGH whenever the read pointer leads the write

pointer by this amount. (See LF4430 Flag application note)