1

Data sheet acquired from Harris Semiconductor

SCHS200

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Positive Edge Clocking

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

Description

The Harris CD74HC4017 is a high speed silicon gate CMOS

5-stage Johnson counter with 10 decoded outputs. Each of

the decoded outputs is normally low and sequentially goes

high on the low to high transition clock period of the 10 clock

period cycle. The CARRY (TC) output transitions low to high

after OUTPUT 10 goes low, and can be used in conjunction

with the CLOCK ENABLE (CE) to cascade several stages.

The CLOCK ENABLE input disables counting when in the

high state. A RESET (MR) input is also provided which when

taken high sets all the decoded outputs, except “0”, low.

The device can drive up to 10 low power Schottky equivalent

loads.

Pinout

CD74HC4017

(PDIP)

TOP VIEW

Ordering Information

PART NUMBER

PACKAGE

PKG.

NO.

CD74HC4017E

-55 to 125

16 Ld PDIP

E16.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

5

1

0

2

6

7

GND

3

CP

CE

TC

9

4

8

MR

November 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1639.1

CD74HC4017

High Speed CMOS Logic

Decade Counter/Divider with 10 Decoded Outputs

[ /Title

(CD74

HC401

7)

/Sub-

ject

(High

Speed

CMOS

Logic

Decade

Counte