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SN74AC564 데이터시트(PDF) 5 Page - Texas Instruments |
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SN74AC564 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 6 page SN54AC564, SN74AC564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS551A – NOVEMBER 1995 – REVISED MAY 1996 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION 50% VCC 0 V 0 V th tsu VOLTAGE WAVEFORMS Data Input tPLH tPHL tPHL tPLH VOH VOH VOL VOL 0 V 50% VCC 50% VCC Input Out-of-Phase Output In-Phase Output Timing Input 50% VCC VOLTAGE WAVEFORMS From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 2 × VCC 500 Ω 500 Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at Open (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ [ VCC 0 V 50% VCC VOL + 0.3 V 50% VCC [ 0 V Open VOLTAGE WAVEFORMS tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open TEST S1 VCC 0 V 50% VCC tw VOLTAGE WAVEFORMS Input 50% VCC 50% VCC 50% VCC VCC 50% VCC 50% VCC VCC VCC 50% VCC 50% VCC 50% VCC VOH – 0.3 V VCC NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms |
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