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SN74AC564DW 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74AC564DW 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 6 page SN54AC564, SN74AC564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS551A – NOVEMBER 1995 – REVISED MAY 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 3-State Inverting Outputs Drive Bus Lines Directly D Full Parallel Access for Loading D Flow-Through Architecture to Optimize PCB Layout D EPIC™ (Enhanced-Performance Implanted CMOS) 1- µm Process D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPs description The ’AC564 are octal D-type edge-triggered flip-flops that feature inverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the inverse logic levels set up at the data (D) inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AC564 is characterized for operation over the full military temperature range of – 55 °C to 125°C. The SN74AC564 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H L L ↑ LH L H or L X Q0 H X X Z 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK SN54AC564 ...J OR W PACKAGE SN74AC564 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2Q 3Q 4Q 5Q 6Q 3D 4D 5D 6D 7D SN54ACT564 . . . FK PACKAGE (TOP VIEW) UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. |
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