SN74ALS679

12-BIT ADDRESS COMPARATOR

SDAS003C – JUNE 1982 – REVISED JANUARY 1995

5

POST OFFICE BOX 655303

APPLICATION INFORMATION

the input pattern for the P inputs. The system address lines that are low in the address to be recognized are connected

to the lowest-numbered A inputs of the address comparator. The system address lines that are high are connected

to the highest-numbered A inputs.

For example, assume the comparator is to enable a device when the 12-bit system address is:

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

H

H

L

L

HH

L

L

HHHH

Because the address contains four lows and eight highs, the following connections are made:

The output provides an active-low enabling signal.

Figure 1 is a register-bank decoder that examines the 14 most significant bits (A0 through A13) of a 20-bit address

to select banks corresponding to the hex addresses 10000, 10040, 10080, and 100C0.

MEMEN

System

Address

Lines

A0 (MSB) – A19

A0 – A2

A4 – A11

A3

A12

A13

A14 – A19

A1 – A11

A12

SN74ALS679

[ADDRESS

COMP]

EN

0

3

P

P0

P1

P2

P3

[P=11]

VCC

G

A

B

1

2

1000016

64 X n-Bit

Registers

S0 – S5

1004016

1008016

100C016

1/2

′ALS139

X/Y

1

2

0

3

1000016

1004016

1008016

100C016

=

=

=

=

LLLH

LLLH

LLLH

LLLH

LLLL

LLLL

LLLL

LLLL

LLLL

LLLL

LLLL

LLLL

LLLL

LHLL

HLLL

HHLL

LLLL

LLLL

LLLL

LLLL

04

8

12

16

11

6

G

Figure 1. Register-Bank Decoder